Semiconductor product operating life test
Semiconductor products are the core in the electronic industry, and the key items of reliability test is related to operating life test for chip. The common experimental projects are performed based on JEDEC 47 or MIL-STD 883. According to JEDEC 47 regulations, the acquisition of samples shall be 3 non-continuous production batches to simulate the stability of production and refer the Family concept to reduce the number of experimental projects and samples.
As for the majority of operating life test, the aging board must be used as the interface between the test machine and the chip. The aging board is the core of the entire test process, and it’s necessary to ensure the stability and avoid additional problems. The common operating life test items are as follows:
Design and manufacture of components on aging board
The design and manufacture of the aging board has been the critical point to the entire life test. Different product classifications and applications may be derived from frequency, transmission speed, signal integrity, heating phenomenon, impedance matching, etc., which are relatively complicated in concerning about the design, material selection, and structure of aging board. VESP Technology Corp. is the only company that can provide one-stop service in design and production of aging boards.
Sampling level
The sampling approach of the reliability life test adopts the LTPD (Lot Tolerance Percent Defective), and the confidence level is generally used at 90%. Both the number of sample selection and the level of confidence will affect the life expectancy, and it shall be noted.
Accelerated life test
High / low temperature life test: the chip is simulated to accelerate aging condition under different temperature through high and low temperature life test that the common acceleration factors are voltage, current, temperature and humidity.
The specification of the high and low temperature life test is referred to the junction temperature (Tj, Junction Temperature) of chip. The consumer and industrial products are applied at high temperature 125 ℃, and low temperature 50 ℃.The time of life test is based on 1000 hours. The actual test time shall be estimated according to customer's product warranty period and service life formula. The life test is a dynamic test. In addition to the acceleration factors mentioned above, a specific program is usually keyed in to ensure that the chip hasn’t occurred any abnormal state exceeding the standard in a dynamic environment, so as to be closer to customers application environment . The following figure shows the framework of the aging test equipment.
Early life failure rate: The purpose of the early life failure rate is to observe the gain for a specific or special product, such as a vehicle product. Another important goal of the early life failure rate is employed to estimate the service life of the product after being shipped to confirm product stability and how many spares need to be prepared for RMA.
The condition of the experiment is same as the actual life test, but the test time is short and there is no abnormal product to be shipped after finishing the test. The figure shows the early life failure rate in the bathtub curve. It can be seen that the problem of the early life failure problem originates from insufficient manufacturing, testing and screening. It is a very important test method to observe the production yield but not just the result of functional test (FT).
VESP Technology Corp. consists of a group of professionals with experienced in semiconductor processes and applications for chip life test. In addition to providing customers with one stop service, there are Taiwan Hsinchu laboratories, Shanghai Zhangjiang laboratories, Shanghai Jinqiao laboratories, Shanghai Pujiang and the Anhui Hefei laboratories to provide various demands of customers. Build up high quality and efficient sales network for customers with customized service and complete service chain.
Customer Service
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