semiconductor verification

ESD/Latch-up Testing

ESD/Latch-up Testing
  Static electricity is a natural phenomenon that occurs in the environment and is caused by an unbalanced distribution of charge in the object. After the object is charged, the charge will remain on the object, so it is called static electricity. After the static electricity is accumulated, when the potential between the objects is different, the charge will pass through the instantaneous current and transfer, that is, discharge.
  The semiconductor product consists of very tiny circuits, and electrostatic discharge protection circuit is designed in integrated circuit in order to prevent chips from being damaged by electrostatic discharge as in production or using. Due to the advanced process development in semiconductor industry, the size of chip has been reduced, and if ESD voltage with stand capacity is upgraded gradually; therefore, electrostatic discharge protection is also regarded as a challenging issue, and ESD test is considered to the critical indicator for quality verification in the early phase of semiconductor product.
Service Items
Human Body Model(HBM) / Machine Model(MM)
Charged Device Model(CDM)
Transmission Line Pulse(TLP)
Product Lifetime Prediction

Categories of ESD Testing

HBM,Human Body Model:This simulates the accumulation of static electricity on the human body caused by walking, friction or other factors. After the person touches the wafer, the static electricity on the human body enters the wafer through the pin, it is then discharged to the ground via the wafer. The current generated at this instant may cause damage to the wafer.

MM,Machine Model:As the machine contacts the chip, static electricity is discharged through the pins with simulating the accumulation of  static electricity on equipment. Because the equivalent resistance of the machine is 0 ohms, it will generate larger current to cause potential damage to chip. However, most of the current standard specifications have canceled the MM electrostatic test mode.

CDM,Charged Device Model:The mode refers to the fact that static electricity has been accumulated in chip owing to friction or other factors, but it has not been damaged in the process of the static electricity accumulation. Therefore, as the chip with static electricity is used, the static electricity in chip will be discharged from the chip through the pin when the pin of the chip contacts the ground, causing a phenomenon of discharge. Moreover, the automotive electronic regulation, AEC-Q100-011, particularly emphasizes the concept of corner pin and indicates that there is a problem of corona discharge. Therefore, the acceptance specification is enhanced in the definition of the test. The acceptance specification of corner pin shall be ≧ 750V, shown as the following figure:

3 types of tests, HBM, MM and CDM comparison chart of discharge time and current: comparison chart of discharge current of static electricity mode for human body (2KV), static electricity mode for machine (200V) and charge mode for component (1KV).


        Latch-up is that instantaneous current is locked or enlarged to cause   (CDM, Charged Device Model): This mode refers to the fact that the chip has accumulated static electricity internally due to friction or other factors, but it has not been damaged during the static electricity accumulation process. Besides, the EOS (Electrical Over Stress) problem that often occurs in customer rejects to be considered in semiconductor industry with latch-up test, so this test has become very important.

The latch-up test mainly refers to the specification of JEDEC 78 and the definition of AEC-Q100-004. In the test of automotive electronics, the definition shall conform to Class II, the maximum ambient temperature condition, which is more rigorous than traditional normal temperature.

Transmission Line Pulse

Transmission Line Pulse (TLP) test is a advanced simulation method for electrostatic discharge of semiconductor products. TLP has obtained an I-V point and increased continuously by employing one pulse condition each time, until the leakage exceeds the specification value.

Snapback phenomena often occur as performing TLP test. There is a t1 trigger point at Vt1 in snapback protection device. As the ESD instantaneous discharge energy continuously supplies the protection device, the characteristic curve of the protection device will get into the snapback area. However, as the ESD instantaneous discharge energy continues to supply the protection device, the characteristic curve of the protection device will also form a low-resistance discharge path to discharge the ESD instantaneous discharge energy. When the voltage and current keep on rising to It2, this is the maximum current that the chip can withstand and also known as the second breakdown point to cause the chip will not restore its original characteristics.


VESP Technology Corp. ESD Lab is possessed of a complete range of services and adopts equipment including MK2, MK4, Orion2, Orion3. At present, it has introduced a new generation of Hanwa ESD test machines from Japan. In addition to Hsinchu in Taiwan, there are service machines in Shanghai Zhangjiang Hi-Tech Park and National Sensor Center in Jiading District, which can provide customers with rapid verification services. Furthermore, TLP has been deployed in Zhangjiang branch of Shanghai that can assist R & D developers to verify the integrity of the ESD protection designs of the chip immediately and help customers products to be launched in the market.

Customer service
Mr. Chang
ESD Testing Enginnering
03-6669700 ext. 6231

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